The present invention will be described with an example application for an Ethernet computer network peripheral device (i.e., a communications network peripheral device) which couples a host computer system to a network of computers (i.e., a communications network). In this example application, the communications network peripheral device issues an interrupt to the host system when the communications network peripheral device has received an information frame, from the communications network, which requires processing by the host system. However, from this example application, it should be appreciated by one of ordinary skill in the art of electronic systems design that the present invention may be practiced for other computer peripheral devices that issue interrupts to the host system.
Referring to FIG. 1, a communications network peripheral device 102 (which may be an Ethernet computer network peripheral device) allows a host computer system 104 to communicate with other computers within a communications network 106 which is comprised of a network of computers. Such a peripheral device 102 receives and transmits information frames on the communications network 106. If the peripheral device 102 is an Ethernet computer network peripheral device, the peripheral device 102 receives and transmits information frames via the communications network 106 in accordance with standard data communications protocols such as the IEEE 802.3 network standard or the DIX Ethernet standard, as is commonly known to one of ordinary skill in the art of Ethernet computer network peripheral device design.
The host system 104 may be a PC or a workstation and includes a CPU (Central Processing Unit) 108. The CPU 108 further processes an information frame from the communications network 106. Referring to FIG. 2, a time line 200 shows an example timing of events when an interrupt is issued by the peripheral device 102 to the CPU 108 of the host system 104.
When the peripheral device 102 receives an information frame from the communications network 106, the peripheral device 102 issues an interrupt to the CPU 108 at time point t.sub.1 to indicate to the CPU 108 that an information frame needs processing by the CPU 108. The CPU 108 is typically in the midst of performing other tasks when such an interrupt is issued, and such other tasks are broadly referred to as the foreground task. Referring to FIG. 2, the CPU 108 is performing a foreground task during time period 202 before the interrupt is issued to the CPU 108 at time point t.sub.1. At this time point t.sub.1, the interrupt bit 204 goes high.
Upon receiving the interrupt at time point t.sub.1, an in-context switching time 206 is spent by the CPU 108 from time point t.sub.1, to time point t.sub.2. During the in-context switching time 206, the CPU 108 transitions from the first foreground task period 202 into an interrupt service routine 208. During the interrupt service routine 208 which is between time point t.sub.2 and time point t.sub.3, the CPU 108 services the interrupt generated by the peripheral device 102. For example, an information frame received by the peripheral device 102 may be processed by the CPU 108. In addition, the interrupt bit 204 is set low after the CPU 108 starts responding to this high-interrupt bit by entering the interrupt service routine 208.
During the in-context switching time 206, the CPU 108 saves any data that will be useful for returning to any foreground tasks after the interrupt service routine 208. The time duration of the in-context switching time 206 is dependent on the type of the CPU 108 and the type of other resources of the host system 104 such as the type of operating system and the type of memory within host system 104.
After the interrupt service routine 208, an out-context switching time 210 is spent by the CPU 108 from time point t.sub.3 to time point t.sub.4. During the out-context switching time 210, the CPU 108 transitions out of the interrupt service routine 208 back to the foreground task 202 at time point t.sub.4. The time duration of the out-context switching time 210 is dependent on the type of the CPU 108 and the type of other resources of the host system 104 such as the type of operating system and the type of memory within host system 104.
Referring to FIG. 3 (with same reference numbers for similar type of time periods of FIG. 2), the interrupt service routine 208 of FIG. 2 is hereinafter designated as a prior interrupt service routine 208 for servicing a prior interrupt 204. A subsequent interrupt 304 may be generated shortly after the prior interrupt service routine 208 during the out-context switching time 210. In that case, the CPU 108 responds to this subsequent interrupt 304 at time point t.sub.4, at the end of the out-context switching time. Then, the CPU 108 enters a subsequent in-context switching time 306 to enter into a subsequent interrupt service routine 308. The signal for the subsequent interrupt 304 turns back low after the CPU starts responding to the subsequent interrupt 304 by entering the subsequent interrupt service routine 308. At the end of the subsequent interrupt service routine 308, a subsequent out-context switching time 310 is spent by the CPU 108 from time point t.sub.6 to time point t.sub.7. During the subsequent out-context switching time 310, the CPU 108 transitions out of the subsequent interrupt service routine 308 back to the foreground task 202 at time point t.sub.7.
Similarly, referring to FIG. 4 (with same reference numbers for similar type of time periods of FIG. 3), the subsequent interrupt 304 may be generated at time point t.sub.4 after the CPU 108 has returned to the foreground task 202. The subsequent interrupt 304 is still generated shortly after the prior out-context switching time 210. Similarly in this case, the CPU 108 enters the subsequent in-context switching time 306 to transition into the subsequent interrupt service routine 308.
In either the case of FIG. 3 or FIG. 4, the subsequent interrupt occurs shortly after the prior interrupt service routine 208. Such situations are likely when a peripheral device asserts a burst of interrupts that are generated closely in time. In FIG. 3 and FIG. 4, the CPU 108 is operating in an interrupt mode and switches contexts between servicing an interrupt and performing a foreground task. In the interrupt mode, the host system 104 incurs overhead usage of the CPU 108 for any in-context switching time and any out-context switching time. This overhead usage of the CPU 108 may be better spent by the CPU 108 for performing foreground tasks. Thus, a mechanism for reducing this overhead usage of the CPU 108 for in-context switching time and out-context switching time is desired.